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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-04 13:15:24 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-04 13:15:24 +0000
commit4c54e8756839e5ba2812ebe812d3542498a6a8a1 (patch)
treecbfba7b20955059dfb682d0b1c6c7ba037aeb713 /hw/ppc4xx_devs.c
parent50bf72b384536e961fd6e433dcfa5c4719201e11 (diff)
downloadqemu-4c54e8756839e5ba2812ebe812d3542498a6a8a1.tar.gz
Remember the state of level-triggered interrupts
(Hollis Blanchard) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4330 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/ppc4xx_devs.c')
-rw-r--r--hw/ppc4xx_devs.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index e87172f298..125f2d43e0 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -278,6 +278,7 @@ typedef struct ppcuic_t ppcuic_t;
struct ppcuic_t {
uint32_t dcr_base;
int use_vectors;
+ uint32_t level; /* Remembers the state of level-triggered interrupts. */
uint32_t uicsr; /* Status register */
uint32_t uicer; /* Enable register */
uint32_t uiccr; /* Critical register */
@@ -385,10 +386,13 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uic->uicsr |= mask;
} else {
/* Level sensitive interrupt */
- if (level == 1)
+ if (level == 1) {
uic->uicsr |= mask;
- else
+ uic->level |= mask;
+ } else {
uic->uicsr &= ~mask;
+ uic->level &= ~mask;
+ }
}
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
@@ -460,6 +464,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
+ uic->uicsr |= uic->level;
ppcuic_trigger_irq(uic);
break;
case DCR_UICSRS: