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authormalc <av1474@comtv.ru>2009-10-01 22:20:47 +0400
committermalc <av1474@comtv.ru>2009-10-01 22:45:02 +0400
commit99a0949b720a0936da2052cb9a46db04ffc6db29 (patch)
treef9e39633853e35b49fc4465337cc196b9650866e /hw/sh_timer.c
parentbc6291a1b95a2c4c546fde6e5cb4c68366f06649 (diff)
downloadqemu-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.gz
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'hw/sh_timer.c')
-rw-r--r--hw/sh_timer.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index fd2146a0c9..057a5076ce 100644
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -57,7 +57,7 @@ static void sh_timer_update(sh_timer_state *s)
s->int_level = new_level;
}
-static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t sh_timer_read(void *opaque, a_target_phys_addr offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;
@@ -77,7 +77,7 @@ static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
}
}
-static void sh_timer_write(void *opaque, target_phys_addr_t offset,
+static void sh_timer_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
sh_timer_state *s = (sh_timer_state *)opaque;
@@ -217,7 +217,7 @@ typedef struct {
int feat;
} tmu012_state;
-static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
+static uint32_t tmu012_read(void *opaque, a_target_phys_addr offset)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -247,7 +247,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
return 0;
}
-static void tmu012_write(void *opaque, target_phys_addr_t offset,
+static void tmu012_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -303,7 +303,7 @@ static CPUWriteMemoryFunc * const tmu012_writefn[] = {
tmu012_write
};
-void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
+void tmu012_init(a_target_phys_addr base, int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
{