summaryrefslogtreecommitdiff
path: root/hw/spapr_pci.h
diff options
context:
space:
mode:
authorAlexey Kardashevskiy <aik@ozlabs.ru>2012-08-07 16:10:37 +0000
committerAlexander Graf <agraf@suse.de>2012-08-15 19:43:16 +0200
commit0ee2c058a3fe485b8901186179102e251a33d082 (patch)
treeacc8e7fb4ba8901e8d5aa3868aa4a88cc123082d /hw/spapr_pci.h
parenta2950fb6e795e3e10fed35d347a7aa28a44be2ff (diff)
downloadqemu-0ee2c058a3fe485b8901186179102e251a33d082.tar.gz
pseries: Add PCI MSI/MSI-X support
This patch implements MSI and MSI-X support for the pseries PCI host bridge. To do this it adds: * A "config_space_address to msi_table" map, since the MSI RTAS calls take a PCI config space address as an identifier. * A MSIX memory region to catch msi_notify()/msix_notiry() from virtio-pci and pass them to the guest via qemu_irq_pulse(). * RTAS call "ibm,change-msi" which sets up MSI vectors for a device. Note that this call may configure and return lesser number of vectors than requested. * RTAS call "ibm,query-interrupt-source-number" which translates MSI vector to interrupt controller (XICS) IRQ number. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix error case ndev < 0] Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/spapr_pci.h')
-rw-r--r--hw/spapr_pci.h15
1 files changed, 13 insertions, 2 deletions
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index 2aee67fd4c..6892e4fae5 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -27,6 +27,8 @@
#include "hw/pci_host.h"
#include "hw/xics.h"
+#define SPAPR_MSIX_MAX_DEVS 32
+
typedef struct sPAPRPHBState {
PCIHostState host_state;
@@ -36,13 +38,22 @@ typedef struct sPAPRPHBState {
MemoryRegion memspace, iospace;
target_phys_addr_t mem_win_addr, mem_win_size, io_win_addr, io_win_size;
- MemoryRegion memwindow, iowindow;
+ target_phys_addr_t msi_win_addr;
+ MemoryRegion memwindow, iowindow, msiwindow;
+
+
DMAContext *dma;
struct {
uint32_t irq;
} lsi_table[PCI_NUM_PINS];
+ struct {
+ uint32_t config_addr;
+ uint32_t irq;
+ int nvec;
+ } msi_table[SPAPR_MSIX_MAX_DEVS];
+
QLIST_ENTRY(sPAPRPHBState) list;
} sPAPRPHBState;
@@ -57,7 +68,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
void spapr_create_phb(sPAPREnvironment *spapr,
const char *busname, uint64_t buid,
uint64_t mem_win_addr, uint64_t mem_win_size,
- uint64_t io_win_addr);
+ uint64_t io_win_addr, uint64_t msi_win_addr);
int spapr_populate_pci_dt(sPAPRPHBState *phb,
uint32_t xics_phandle,