Sparc32: improve interrupt handling

Level 15 interrupts are broadcast to all CPUs, each CPU can clear the
interrupt using the local Clear Pending register.

Update intbit_to_level table.

Don't try to raise level 0 interrupts.

Calculate pending interrupts based on the separate inputs from master
register. Setting or resetting the pending level isn't correct because of
overlap of levels.

Level 14 is always used for CPU timer interrupts, remove the property.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

1 files changed, 2 insertions, 5 deletions

diff --git a/hw/sun4m.c b/hw/sun4m.c
index 88a0b2511d..17854dbbd2 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -396,15 +396,13 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
 
 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
                                        target_phys_addr_t addrg,
-                                       qemu_irq **parent_irq,
-                                       unsigned int cputimer)
+                                       qemu_irq **parent_irq)
 {
     DeviceState *dev;
     SysBusDevice *s;
     unsigned int i, j;
 
     dev = qdev_create(NULL, "slavio_intctl");
-    qdev_prop_set_uint32(dev, "cputimer_bit", cputimer);
     qdev_init(dev);
 
     s = sysbus_from_qdev(dev);
@@ -769,8 +767,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
 
     slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
                                        hwdef->intctl_base + 0x10000ULL,
-                                       cpu_irqs,
-                                       7);
+                                       cpu_irqs);
 
     for (i = 0; i < 32; i++) {
         slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);