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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-06-11 11:00:40 +1000
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2013-06-18 09:45:00 +0200
commitafd59989db90683fa127fec501d2633bcfbd6379 (patch)
treed77f253eaeedb040c4fa7da13c67ad0ca0d22ac7 /hw
parentfa96d6142f7f1947717c7c45c4d3141e5ab55167 (diff)
downloadqemu-afd59989db90683fa127fec501d2633bcfbd6379.tar.gz
intc/xilinx_intc: Dont lower IRQ when HIE cleared
This is a little strange. It is lowering the parent IRQ pin on input when HIE is cleared. There is no such behaviour in the real hardware. ISR changes based on interrupt pin state are already guarded on HIE being set. So we can just delete this if in its entirety. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/intc/xilinx_intc.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index ddedfa3796..297f53759c 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -143,11 +143,6 @@ static void irq_handler(void *opaque, int irq, int level)
{
struct xlx_pic *p = opaque;
- if (!(p->regs[R_MER] & 2)) {
- qemu_irq_lower(p->parent_irq);
- return;
- }
-
/* edge triggered interrupt */
if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
p->regs[R_ISR] |= (level << irq);