diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-25 11:55:15 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-29 15:19:22 +0100 |
| commit | 51e08f3e4b8a3b6d27fde9a9e75c8fa32eaa72d0 (patch) | |
| tree | cfdfc4c13300191c3982e6bb026ba09ea5dba705 /hw | |
| parent | c29cd656a8fad633fb9ca45b88ade9838d35fd5c (diff) | |
| download | qemu-51e08f3e4b8a3b6d27fde9a9e75c8fa32eaa72d0.tar.gz | |
mc146818rtc: update registers after a format change
For some unknown reason, the MIPS kernel briefly changes the RTC to
binary mode during boot, switch back to BCD mode and read the time. As
the registers are updated only every second, they may still be in the
old format when they are read.
This patch forces a register update immediately after a format change
(BCD/binary or 12/24H). This avoid long fsck during boot due to time
wrap.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/mc146818rtc.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index ec7c4ecdb6..a1b0e31ee5 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -247,7 +247,15 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) rtc_set_time(s); } } - s->cmos_data[RTC_REG_B] = data; + if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) && + !(data & REG_B_SET)) { + /* If the time format has changed and not in set mode, + update the registers immediately. */ + s->cmos_data[RTC_REG_B] = data; + rtc_copy_date(s); + } else { + s->cmos_data[RTC_REG_B] = data; + } rtc_timer_update(s, qemu_get_clock(rtc_clock)); break; case RTC_REG_C: |