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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 17:50:57 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 17:50:57 +0000 |
| commit | 536b558f5896ebbd635b57fa393e82faaa32ad52 (patch) | |
| tree | 61756309c1d8f338f943f69bfbe6e6e50128da92 /hw | |
| parent | 511c68d3af626cb0a39034cb77e7ac64d3a26c0c (diff) | |
| parent | 19e6c50d2d843220efbdd3b2db21d83c122c364a (diff) | |
| download | qemu-536b558f5896ebbd635b57fa393e82faaa32ad52.tar.gz | |
Merge branch 'master' of git.qemu-project.org:/pub/git/qemu
* 'master' of git.qemu-project.org:/pub/git/qemu:
target-mips: Fix incorrect shift for SHILO and SHILOV
target-mips: Fix incorrect code and test for INSV
xilinx_uartlite: Accept input after rx FIFO pop
xilinx_uartlite: suppress "cannot receive message"
xilinx_axienet: Implement R_IS behaviour
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/xilinx_axienet.c | 4 | ||||
| -rw-r--r-- | hw/xilinx_uartlite.c | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c index baae02bd66..f2e3bf1274 100644 --- a/hw/xilinx_axienet.c +++ b/hw/xilinx_axienet.c @@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr, s->maddr[s->fmi & 3][addr & 1] = value; break; + case R_IS: + s->regs[addr] &= ~value; + break; + case 0x8000 ... 0x83ff: s->ext_mtable[addr - 0x8000] = value; break; diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c index d20fc4124b..02c5850331 100644 --- a/hw/xilinx_uartlite.c +++ b/hw/xilinx_uartlite.c @@ -97,6 +97,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) s->rx_fifo_len--; uart_update_status(s); uart_update_irq(s); + qemu_chr_accept_input(s->chr); break; default: @@ -182,12 +183,8 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) static int uart_can_rx(void *opaque) { struct xlx_uartlite *s = opaque; - int r; - r = s->rx_fifo_len < sizeof(s->rx_fifo); - if (!r) - printf("cannot receive!\n"); - return r; + return s->rx_fifo_len < sizeof(s->rx_fifo); } static void uart_event(void *opaque, int event) |