diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-12-11 11:30:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-12-11 11:30:37 +0000 |
| commit | cad065f18e1ca7694385f42f560da637d4e651b6 (patch) | |
| tree | bfba72e964d262655842c525b03cc1f1d0543203 /hw | |
| parent | bf471f7950e9dc9416747b2774eb712f63afe5a7 (diff) | |
| download | qemu-cad065f18e1ca7694385f42f560da637d4e651b6.tar.gz | |
hw/arm_gic: Fix comparison with priority mask register
The GIC spec states that only interrupts with higher priority
than the value in the GICC_PMR priority mask register are
passed through to the processor. We were incorrectly allowing
through interrupts with a priority equal to the specified
value: correct the comparison operation to match the spec.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm_gic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index f9e423f152..672d539996 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -73,7 +73,7 @@ void gic_update(GICState *s) } } level = 0; - if (best_prio <= s->priority_mask[cpu]) { + if (best_prio < s->priority_mask[cpu]) { s->current_pending[cpu] = best_irq; if (best_prio < s->running_priority[cpu]) { DPRINTF("Raised pending IRQ %d\n", best_irq); |