diff options
| author | Leonid Bloch <leonid.bloch@ravellosystems.com> | 2015-11-11 15:52:43 +0200 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2015-11-12 15:26:53 +0800 |
| commit | 1f67f92c4fdf59a98c2fdf67d3e78deba489a370 (patch) | |
| tree | 54e1e0070e00d131bf88c38620770841f6094184 /hw | |
| parent | 72ea771c9711cba63686d5d3284bc6645d13f7d2 (diff) | |
| download | qemu-1f67f92c4fdf59a98c2fdf67d3e78deba489a370.tar.gz | |
e1000: Fixing the received/transmitted packets' counters
According to Intel's specs, these counters (as the other Statistic
registers) stick at 0xffffffff when this maximal value is reached.
Previously, they would reset after the max. value.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/net/e1000.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 767490cef5..57a61f6e35 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -580,6 +580,14 @@ putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) } } +static inline void +inc_reg_if_not_full(E1000State *s, int index) +{ + if (s->mac_reg[index] != 0xffffffff) { + s->mac_reg[index]++; + } +} + static inline int vlan_enabled(E1000State *s) { @@ -677,8 +685,8 @@ xmit_seg(E1000State *s) e1000_send_packet(s, tp->data, tp->size); } - s->mac_reg[TPT]++; - s->mac_reg[GPTC]++; + inc_reg_if_not_full(s, TPT); + s->mac_reg[GPTC] = s->mac_reg[TPT]; n = s->mac_reg[TOTL]; if ((s->mac_reg[TOTL] += s->tx.size) < n) s->mac_reg[TOTH]++; @@ -1091,8 +1099,8 @@ e1000_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) } } while (desc_offset < total_size); - s->mac_reg[GPRC]++; - s->mac_reg[TPR]++; + inc_reg_if_not_full(s, TPR); + s->mac_reg[GPRC] = s->mac_reg[TPR]; /* TOR - Total Octets Received: * This register includes bytes received in a packet from the <Destination * Address> field through the <CRC> field, inclusively. |