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| author | Michael Clark <mjc@sifive.com> | 2018-03-03 14:30:07 +1300 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-06 10:39:38 +1200 |
| commit | 2a8756ed7d64f8fed6ad50fb062f7118e47c856c (patch) | |
| tree | e51ad53bef7471fad7c2ae36bc48ccf483a56238 /include/hw/riscv/spike.h | |
| parent | c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9 (diff) | |
| download | qemu-2a8756ed7d64f8fed6ad50fb062f7118e47c856c.tar.gz | |
RISC-V: Replace hardcoded constants with enum values
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/spike.h')
| -rw-r--r-- | include/hw/riscv/spike.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cb55a14d30..d85a64e33d 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -42,6 +42,10 @@ enum { SPIKE_DRAM }; +enum { + SPIKE_CLOCK_FREQ = 1000000000 +}; + #if defined(TARGET_RISCV32) #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 |