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| author | Richard Henderson <rth@twiddle.net> | 2012-09-21 10:34:21 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2012-09-21 22:02:16 +0200 |
| commit | 9b9c37c36439ee0452632253dac7a31897f27f70 (patch) | |
| tree | b5c8fa6937fcc7a4d2f75cd64051f66d6bbfc25b /qemu-timer.h | |
| parent | d5dd696fe3049657c08eb14f40cb74b6e94e79cc (diff) | |
| download | qemu-9b9c37c36439ee0452632253dac7a31897f27f70.tar.gz | |
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Since
no one really noticed, drop the complication of v7 and v8 cpus.
Eliminate the --sparc_cpu configure option and standardize macro
testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'qemu-timer.h')
| -rw-r--r-- | qemu-timer.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/qemu-timer.h b/qemu-timer.h index f8af595f13..da7e97cd5a 100644 --- a/qemu-timer.h +++ b/qemu-timer.h @@ -218,7 +218,7 @@ static inline int64_t cpu_get_real_ticks(void) return val; } -#elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__) +#elif defined(__sparc__) static inline int64_t cpu_get_real_ticks (void) { @@ -227,6 +227,8 @@ static inline int64_t cpu_get_real_ticks (void) asm volatile("rd %%tick,%0" : "=r"(rval)); return rval; #else + /* We need an %o or %g register for this. For recent enough gcc + there is an "h" constraint for that. Don't bother with that. */ union { uint64_t i64; struct { @@ -234,8 +236,8 @@ static inline int64_t cpu_get_real_ticks (void) uint32_t low; } i32; } rval; - asm volatile("rd %%tick,%1; srlx %1,32,%0" - : "=r"(rval.i32.high), "=r"(rval.i32.low)); + asm volatile("rd %%tick,%%g1; srlx %%g1,32,%0; mov %%g1,%1" + : "=r"(rval.i32.high), "=r"(rval.i32.low) : : "g1"); return rval.i64; #endif } |