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author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:18 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:08:16 +0000 |
commit | 34f9052967b2495c524560906023dbebf6556b5d (patch) | |
tree | 367e1396e70e416545e62479357dc09f2c1f34b1 /slirp | |
parent | 06d76f319f2ea1cf8a66392670a04f649d6280ce (diff) | |
download | qemu-34f9052967b2495c524560906023dbebf6556b5d.tar.gz |
target-arm: Convert cp15 crn=9 registers
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.
Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is
a change from previous behaviour, but a return to the behaviour of commit
c3d2689d when OMAP1 support was first added -- subsequent commits have
clearly accidentally relegated the OMAPCP RAZ condition to only a subset of
the crn=9 space when adding support for other cores.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'slirp')
0 files changed, 0 insertions, 0 deletions