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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-29 00:22:01 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-29 00:22:01 +0000 |
| commit | b5d51029042aa7da6a376d39adedb00da9227efe (patch) | |
| tree | 5a1c8c3d35f15bb4a03576599c706dc1ffc96a7e /target-alpha | |
| parent | f8cc85341531b4c9cacd2fc199f984b09a073258 (diff) | |
| download | qemu-b5d51029042aa7da6a376d39adedb00da9227efe.tar.gz | |
target-alpha: add instruction name in comments for hw_ld opcode.
Make code slightly easier to read.
Also unused hw_ld opcodes now generate an invalid opc fault.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6928 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-alpha')
| -rw-r--r-- | target-alpha/translate.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 91f2387cce..8bdec80fbc 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1793,62 +1793,62 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) tcg_gen_movi_i64(addr, disp12); switch ((insn >> 12) & 0xF) { case 0x0: - /* Longword physical access */ + /* Longword physical access (hw_ldl/p) */ gen_helper_ldl_raw(cpu_ir[ra], addr); break; case 0x1: - /* Quadword physical access */ + /* Quadword physical access (hw_ldq/p) */ gen_helper_ldq_raw(cpu_ir[ra], addr); break; case 0x2: - /* Longword physical access with lock */ + /* Longword physical access with lock (hw_ldl_l/p) */ gen_helper_ldl_l_raw(cpu_ir[ra], addr); break; case 0x3: - /* Quadword physical access with lock */ + /* Quadword physical access with lock (hw_ldq_l/p) */ gen_helper_ldq_l_raw(cpu_ir[ra], addr); break; case 0x4: - /* Longword virtual PTE fetch */ - gen_helper_ldl_kernel(cpu_ir[ra], addr); + /* Longword virtual PTE fetch (hw_ldl/v) */ + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); break; case 0x5: - /* Quadword virtual PTE fetch */ - gen_helper_ldq_kernel(cpu_ir[ra], addr); + /* Quadword virtual PTE fetch (hw_ldq/v) */ + tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); break; case 0x6: /* Incpu_ir[ra]id */ - goto incpu_ir[ra]id_opc; + goto invalid_opc; case 0x7: /* Incpu_ir[ra]id */ - goto incpu_ir[ra]id_opc; + goto invalid_opc; case 0x8: - /* Longword virtual access */ + /* Longword virtual access (hw_ldl) */ gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldl_raw(cpu_ir[ra], addr); break; case 0x9: - /* Quadword virtual access */ + /* Quadword virtual access (hw_ldq) */ gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldq_raw(cpu_ir[ra], addr); break; case 0xA: - /* Longword virtual access with protection check */ - tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags); + /* Longword virtual access with protection check (hw_ldl/w) */ + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); break; case 0xB: - /* Quadword virtual access with protection check */ - tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags); + /* Quadword virtual access with protection check (hw_ldq/w) */ + tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); break; case 0xC: - /* Longword virtual access with altenate access mode */ + /* Longword virtual access with alt access mode (hw_ldl/a)*/ gen_helper_set_alt_mode(); gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldl_raw(cpu_ir[ra], addr); gen_helper_restore_mode(); break; case 0xD: - /* Quadword virtual access with altenate access mode */ + /* Quadword virtual access with alt access mode (hw_ldq/a) */ gen_helper_set_alt_mode(); gen_helper_st_virt_to_phys(addr, addr); gen_helper_ldq_raw(cpu_ir[ra], addr); @@ -1856,7 +1856,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0xE: /* Longword virtual access with alternate access mode and - * protection checks + * protection checks (hw_ldl/wa) */ gen_helper_set_alt_mode(); gen_helper_ldl_data(cpu_ir[ra], addr); @@ -1864,7 +1864,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0xF: /* Quadword virtual access with alternate access mode and - * protection checks + * protection checks (hw_ldq/wa) */ gen_helper_set_alt_mode(); gen_helper_ldq_data(cpu_ir[ra], addr); |