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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:49 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:06 +0100 |
| commit | f318cec6adcb73c688d68b0874686a30c0f34a2e (patch) | |
| tree | fa722ad17c8c35c4fae6391bbd88f007c25e2b9b /target-arm/cpu-qom.h | |
| parent | 377a44ec8f2fac5b7bef41d212dfbabf53c8c810 (diff) | |
| download | qemu-f318cec6adcb73c688d68b0874686a30c0f34a2e.tar.gz | |
target-arm: Implement CBAR for Cortex-A57
The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view; expand the QOM reset-cbar property from UINT32
to UINT64 so this can be specified, and implement the
32-bit and 64-bit views of a 64-bit CBAR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu-qom.h')
| -rw-r--r-- | target-arm/cpu-qom.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 743985ec2d..82f1bc7173 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -148,7 +148,7 @@ typedef struct ARMCPU { * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ uint32_t ccsidr[16]; - uint32_t reset_cbar; + uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |