diff options
| author | Alexander Graf <agraf@suse.de> | 2013-09-03 20:12:09 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-09-10 19:11:28 +0100 |
| commit | 3926cc8433542e8c9b7cdc438355fb7660838fd0 (patch) | |
| tree | e9f54a33589c0828be150d85d0193bf5d6c9cad1 /target-arm/cpu.c | |
| parent | 15ee776bf2001883781cc83d456249a60532bb01 (diff) | |
| download | qemu-3926cc8433542e8c9b7cdc438355fb7660838fd0.tar.gz | |
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn't
fit into split up patches. It extends important bits in the core cpu
headers to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag
indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org
[PMM:
* rearranged tbflags so AArch64? is bit 31 and if it is set then
30..0 are freely available for whatever makes most sense for that mode
* added version bump since we change VFP migration state
* added a comment about how VFP/Neon register state works
* physical address space is 48 bits, not 64
* added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index e8faadb209..d40f2a7a4f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -84,6 +84,11 @@ static void arm_cpu_reset(CPUState *s) env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; } + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* 64 bit CPUs always start in 64 bit mode */ + env->aarch64 = 1; + } + #if defined(CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ @@ -834,6 +839,9 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); +#ifdef TARGET_AARCH64 + set_feature(&cpu->env, ARM_FEATURE_AARCH64); +#endif cpu->midr = 0xffffffff; } #endif |