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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-04-20 17:58:35 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-04-21 18:12:29 +0000 |
| commit | 85df3786b21191d49d17dcb77f45ae75f6addad0 (patch) | |
| tree | e075ad99853625aa15939dc554427d713479945d /target-arm/cpu.c | |
| parent | 8092d2f031e70eb2664d5fa1d9ed00ef1113ee71 (diff) | |
| download | qemu-85df3786b21191d49d17dcb77f45ae75f6addad0.tar.gz | |
target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 333f7fc161..8259a0df43 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -270,6 +270,10 @@ static void cortex_a8_initfn(Object *obj) cpu->id_isar2 = 0x21232031; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x00111142; + cpu->clidr = (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ } static void cortex_a9_initfn(Object *obj) @@ -304,6 +308,9 @@ static void cortex_a9_initfn(Object *obj) cpu->id_isar2 = 0x21232041; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x00111142; + cpu->clidr = (1 << 27) | (1 << 24) | 3; + cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ } static void cortex_a15_initfn(Object *obj) @@ -336,6 +343,10 @@ static void cortex_a15_initfn(Object *obj) cpu->id_isar2 = 0x21232041; cpu->id_isar3 = 0x11112131; cpu->id_isar4 = 0x10011142; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ } static void ti925t_initfn(Object *obj) |