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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:17 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:08:11 +0000 |
| commit | 06d76f319f2ea1cf8a66392670a04f649d6280ce (patch) | |
| tree | 49038686dbf9fb3d5e68b0d8cce79b1a9f6df66f /target-arm/cpu.c | |
| parent | c480421426c984068a27502c2948d2fa51b8cf96 (diff) | |
| download | qemu-06d76f319f2ea1cf8a66392670a04f649d6280ce.tar.gz | |
target-arm: Convert cp15 crn=6 registers
Convert the cp15 crn=6 registers to the new scheme.
Note that this includes some minor tidyup: drop an unnecessary
underdecoding of op2 on OMAPCP cores, and only implement the
pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5
cores, which didn't have it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f8534a78b3..f37380ffe1 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -251,6 +251,16 @@ static void arm1026_initfn(Object *obj) cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; + { + /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ + ARMCPRegInfo ifar = { + .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), + .resetvalue = 0 + }; + define_one_arm_cp_reg(cpu, &ifar); + } } static void arm1136_r2_initfn(Object *obj) |