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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-08-13 11:26:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-08-13 11:26:22 +0100 |
| commit | b4d3978c2fdf944e428a46d2850dbd950b6fbe78 (patch) | |
| tree | cad66422e4c81b720274cec302bcc5eda6c471af /target-arm/cpu.c | |
| parent | 49a661910c1374858602a3002b67115893673c25 (diff) | |
| download | qemu-b4d3978c2fdf944e428a46d2850dbd950b6fbe78.tar.gz | |
target-arm: Add the AArch64 view of the Secure physical timer
On CPUs with EL3, there are two physical timers, one for Secure and one
for Non-secure. Implement this extra timer and the AArch64 registers
which access it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 3c84f72928..cc6c6f3d4c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -478,6 +478,8 @@ static void arm_cpu_initfn(Object *obj) arm_gt_vtimer_cb, cpu); cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, + arm_gt_stimer_cb, cpu); qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, ARRAY_SIZE(cpu->gt_timer_outputs)); #endif |