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| author | Rob Herring <rob.herring@linaro.org> | 2014-04-15 19:18:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:04 +0100 |
| commit | 6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03 (patch) | |
| tree | 7b46494b34d745af65a5463a419a92a6e1bc011d /target-arm/cpu.h | |
| parent | 7e09797c299712cafa7bc05dd57c1b13afcc6039 (diff) | |
| download | qemu-6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03.tar.gz | |
target-arm: Implement AArch64 views of fault status and data registers
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit
DFSR, DFAR, IFAR share state with them as architecturally specified.
The IFSR doesn't share state with any AArch64 register visible at EL1,
so just rename the state field without widening it to 64 bits.
Signed-off-by: Rob Herring <rob.herring@linaro.org>
[PMM: Minor tweaks; fix some bugs involving inconsistencies between
use of offsetof() or offsetoflow32() and struct field width]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 42fa7db433..4ca75cd91d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,11 +181,10 @@ typedef struct CPUARMState { MPU write buffer control. */ uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ - uint32_t c5_insn; /* Fault status registers. */ - uint32_t c5_data; + uint32_t ifsr_el2; /* Fault status registers. */ + uint64_t esr_el1; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint32_t c6_insn; /* Fault address registers. */ - uint32_t c6_data; + uint64_t far_el1; /* Fault address registers. */ uint32_t c7_par; /* Translation result. */ uint32_t c7_par_hi; /* Translation result, high 32 bits */ uint32_t c9_insn; /* Cache lockdown registers. */ |