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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-12-11 12:07:51 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-11 12:07:51 +0000 |
| commit | 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b (patch) | |
| tree | 9d41dc245d0e9b434291ef122af802110ec26cbd /target-arm/cpu.h | |
| parent | 88ca1c2d70523486a952065f3ed7b8fc823b5863 (diff) | |
| download | qemu-4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b.tar.gz | |
target-arm: make DFSR banked
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-21-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e8bb057ffc..29870bda4e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -251,7 +251,15 @@ typedef struct CPUARMState { uint64_t ifsr32_el2; }; }; - uint64_t esr_el[4]; + union { + struct { + uint64_t _unused_dfsr; + uint64_t dfsr_ns; + uint64_t hsr; + uint64_t dfsr_s; + }; + uint64_t esr_el[4]; + }; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ |