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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:04 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:04 +0000 |
| commit | 327ed10fa2331384c1a58c794e0356e6d88089c8 (patch) | |
| tree | 7c0a3f3bc6e638a341800158846f35f0eb4964d5 /target-arm/cpu.h | |
| parent | a505d7fe5f638c4aaba93150f71968147f7c2b3a (diff) | |
| download | qemu-327ed10fa2331384c1a58c794e0356e6d88089c8.tar.gz | |
target-arm: Implement AArch64 TTBR*
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the architectural name.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 06953ac9bd..4bbc9ad548 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -173,10 +173,8 @@ typedef struct CPUARMState { uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ - uint32_t c2_base0; /* MMU translation table base 0. */ - uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */ - uint32_t c2_base1; /* MMU translation table base 0. */ - uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */ + uint64_t ttbr0_el1; /* MMU translation table base 0. */ + uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ uint32_t c2_mask; /* MMU translation table base selection mask. */ uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ |