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| author | Mark Langsdorf <mark.langsdorf@calxeda.com> | 2012-01-05 15:49:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-01-05 15:49:06 +0000 |
| commit | 7da362d01644fca96c7cb4b72dbf2510020061f2 (patch) | |
| tree | a9b37bcfdf501b8b717d105118baa7dcb65adf98 /target-arm/cpu.h | |
| parent | 37064a8b6f9075e18b05bfc6d5264b138a224713 (diff) | |
| download | qemu-7da362d01644fca96c7cb4b72dbf2510020061f2.tar.gz | |
arm: add dummy A9-specific cp15 registers
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c4d742f084..26b4981fdd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -149,6 +149,10 @@ typedef struct CPUARMState { uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ uint32_t c15_threadid; /* TI debugger thread-ID. */ + uint32_t c15_config_base_address; /* SCU base address. */ + uint32_t c15_diagnostic; /* diagnostic register */ + uint32_t c15_power_diagnostic; + uint32_t c15_power_control; /* power control */ } cp15; struct { @@ -448,7 +452,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 4 +#define CPU_SAVE_VERSION 5 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |