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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:04 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:04 +0000 |
| commit | a505d7fe5f638c4aaba93150f71968147f7c2b3a (patch) | |
| tree | fff3c44869f59c007446e4d6c1e130da13863208 /target-arm/cpu.h | |
| parent | cb2e37dffaab38e962b86b3ca6f4cf0de22d9e69 (diff) | |
| download | qemu-a505d7fe5f638c4aaba93150f71968147f7c2b3a.tar.gz | |
target-arm: Implement AArch64 VBAR_EL1
Implement the A64 view of the VBAR system register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4e87064920..06953ac9bd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -200,7 +200,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint32_t c12_vbar; /* vector base address register */ + uint64_t c12_vbar; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_context; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ |