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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-01-31 20:45:13 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-01-31 20:45:13 +0000 |
| commit | 99c475abf16b10923baac09682a9d801ae421ac6 (patch) | |
| tree | 3e1d1433c7f6f6e530bf50577625df75eb03274e /target-arm/cpu.h | |
| parent | dfe86665b8d61659f2c24f7365f75fe89f4705ac (diff) | |
| download | qemu-99c475abf16b10923baac09682a9d801ae421ac6.tar.gz | |
armv5te support (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1258 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7d34766b7e..d754512811 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -35,6 +35,9 @@ typedef struct CPUARMState { uint32_t CF; /* 0 or 1 */ uint32_t VF; /* V is the bit 31. All other bits are undefined */ uint32_t NZF; /* N is bit 31. Z is computed from NZF */ + uint32_t QF; /* 0 or 1 */ + + int thumb; /* 0 = arm mode, 1 = thumb mode */ /* exception/interrupt handling */ jmp_buf jmp_env; |