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| author | Rob Herring <rob.herring@calxeda.com> | 2012-01-13 17:25:08 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-01-13 17:25:08 +0000 |
| commit | 2be276242135eac6e86be2a8259545e620c94107 (patch) | |
| tree | 19d69cd0f75acdfdafdf9b16915272fd69037df4 /target-arm/cpu.h | |
| parent | d3cb6e2b062f69e0a40f21b74a42f5c5a3422174 (diff) | |
| download | qemu-2be276242135eac6e86be2a8259545e620c94107.tar.gz | |
arm: Add dummy support for co-processor 15's secure config register
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 26b4981fdd..42c53a7d52 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -116,6 +116,7 @@ typedef struct CPUARMState { uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t c1_scr; /* secure config register. */ uint32_t c2_base0; /* MMU translation table base 0. */ uint32_t c2_base1; /* MMU translation table base 1. */ uint32_t c2_control; /* MMU translation table base control. */ @@ -452,7 +453,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 5 +#define CPU_SAVE_VERSION 6 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |