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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-29 00:20:44 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-29 00:20:44 +0000
commitfbb4a2e371f2fa7d3bbe479795d8c79a795f7cd3 (patch)
tree7ac6203fe8fd1adb8b844da4073ae7919bfe83a2 /target-arm/cpu.h
parentce5232c5c281552039466be5eadf93a712eb7611 (diff)
downloadqemu-fbb4a2e371f2fa7d3bbe479795d8c79a795f7cd3.tar.gz
Implement ARM magic kernel page and TLS register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c26cad28b6..f7252f5c21 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -38,6 +38,7 @@
#define EXCP_FIQ 6
#define EXCP_BKPT 7
#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
+#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
@@ -216,6 +217,10 @@ int cpu_arm_signal_handler(int host_signum, void *pinfo,
void cpu_lock(void);
void cpu_unlock(void);
+static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
+{
+ env->cp15.c13_tls2 = newtls;
+}
#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)