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| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-19 13:37:53 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-19 13:37:53 +0000 |
| commit | a49ea279c4fcda7e6558bfe5b32a8d9aff0dd05b (patch) | |
| tree | da6b005397596cda89d55c8ec49a6039088f5d4b /target-arm/cpu.h | |
| parent | fe1479c3ad177df09d465338d5421a5f3b857f91 (diff) | |
| download | qemu-a49ea279c4fcda7e6558bfe5b32a8d9aff0dd05b.tar.gz | |
Implement ARMv7 cp15 cache ID registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 84d7aa9529..ab101c9d78 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -100,6 +100,9 @@ typedef struct CPUARMState { struct { uint32_t c0_cpuid; uint32_t c0_cachetype; + uint32_t c0_ccsid[16]; /* Cache size. */ + uint32_t c0_clid; /* Cache level. */ + uint32_t c0_cssel; /* Cache size selection. */ uint32_t c0_c1[8]; /* Feature registers. */ uint32_t c0_c2[8]; /* Instruction set registers. */ uint32_t c1_sys; /* System control register. */ |