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| author | Peter Maydell <peter.maydell@linaro.org> | 2013-08-20 14:54:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-08-20 14:54:28 +0100 |
| commit | 7c1840b686e34ed138414ff0fe395a63f031387e (patch) | |
| tree | 8ebb9da43ec797b4fa5683de41624dba9c7d8105 /target-arm/cpu.h | |
| parent | 3f1beaca88bffa4828cc86beb89ff70474516d91 (diff) | |
| download | qemu-7c1840b686e34ed138414ff0fe395a63f031387e.tar.gz | |
target-arm: Make IRQ and FIQ gpio lines on the CPU object
Now that ARMCPU is a subclass of DeviceState, we can make the
CPU's inbound IRQ and FIQ lines be simply gpio lines, which
means we can remove the odd arm_pic shim.
We retain the arm_pic_init_cpu() function as a backwards
compatibility shim layer so we can convert the board models
to get the IRQ and FIQ lines directly from the ARMCPU
object one at a time.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1375977856-25046-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index b2dc49413c..dffeec7455 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -58,6 +58,9 @@ /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 +/* Meanings of the ARMCPU object's two inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 typedef void ARMWriteCPFunc(void *opaque, int cp_info, int srcreg, int operand, uint32_t value); |