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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:20 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:10:54 +0000 |
| commit | 81bdde9dcdba5bbc358b2c6b8f776a05a751cc72 (patch) | |
| tree | 089fdb29b16a895498f2a6a14926f05fa8007b07 /target-arm/cpu.h | |
| parent | 776d4e5c6ca47f8d7b73c9c8eccf20209bf57529 (diff) | |
| download | qemu-81bdde9dcdba5bbc358b2c6b8f776a05a751cc72.tar.gz | |
target-arm: Convert MPIDR
Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0b984d8495..2630fe7739 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -386,6 +386,7 @@ enum arm_features { ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ + ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ }; static inline int arm_feature(CPUARMState *env, int feature) |