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| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-10-22 19:22:30 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-10-22 19:22:30 +0000 |
| commit | b2fa17977f3e9b7ced2cbbe14f6d3c4b3e8e314e (patch) | |
| tree | b9f94ee9f7b9a54cd37fa8a2c6d4aca7cd77f97a /target-arm/cpu.h | |
| parent | 83c1f87cc8f865f1f55a2e476cd827aa51089e8c (diff) | |
| download | qemu-b2fa17977f3e9b7ced2cbbe14f6d3c4b3e8e314e.tar.gz | |
Fix ARMv6 translation table base address calculation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ff765f7838..c18224510b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -107,7 +107,9 @@ typedef struct CPUARMState { uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c2_base0; /* MMU translation table base 0. */ uint32_t c2_base1; /* MMU translation table base 1. */ - uint32_t c2_mask; /* MMU translation table base mask. */ + uint32_t c2_control; /* MMU translation table base control. */ + uint32_t c2_mask; /* MMU translation table base selection mask. */ + uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register |