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| author | Alex Bennée <alex.bennee@linaro.org> | 2014-03-17 16:31:52 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:52 +0000 |
| commit | b6d4443a7bf607c5ca5d4b8dabffc421e571f4eb (patch) | |
| tree | 34110bfb27348b7adbabcff3eecfd75aff0d2dd3 /target-arm/helper.h | |
| parent | 7baeabce1d25c667d0ec7e4e74a1312e0b887b54 (diff) | |
| download | qemu-b6d4443a7bf607c5ca5d4b8dabffc421e571f4eb.tar.gz | |
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
Implement URECPE and FRECPE instructions in both scalar and vector forms.
The actual reciprocal estimate function is shared with the A32/T32 Neon
code. However in A64 we aren't using the Neon "standard FPSCR value"
so extra checks are necessary to handle non-squashed denormal inputs
which can never happen for A32/T32. Calling conventions for the helpers
are thus modified to pass the fpst directly; we mark the helpers as
TCG_CALL_NO_RWG since we're changing the declarations anyway.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.h')
| -rw-r--r-- | target-arm/helper.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target-arm/helper.h b/target-arm/helper.h index 8923f8ae71..f96a82415a 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -167,9 +167,10 @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) DEF_HELPER_3(recps_f32, f32, f32, f32, env) DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) -DEF_HELPER_2(recpe_f32, f32, f32, env) +DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_2(rsqrte_f32, f32, f32, env) -DEF_HELPER_2(recpe_u32, i32, i32, env) +DEF_HELPER_2(recpe_u32, i32, i32, ptr) DEF_HELPER_2(rsqrte_u32, i32, i32, env) DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) |