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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-04-01 17:57:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-04-01 17:57:29 +0100 |
| commit | 7847f9ea9fce15a9ecfb62ab72c1e84ff516b0db (patch) | |
| tree | 57af085d325a3b98ff097c385a4c1d5ff8e0bc56 /target-arm/internals.h | |
| parent | 4de9a883be653f02f8c1d5dcd1066f614d9606b6 (diff) | |
| download | qemu-7847f9ea9fce15a9ecfb62ab72c1e84ff516b0db.tar.gz | |
target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env->banked_spsr[1] field.
Correct the various places in the code that incorrectly
put it in banked_spsr[0].
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/internals.h')
| -rw-r--r-- | target-arm/internals.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h index bb171a73bd..2cc301762c 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -82,11 +82,14 @@ static inline void arm_log_exception(int idx) /* * For AArch64, map a given EL to an index in the banked_spsr array. + * Note that this mapping and the AArch32 mapping defined in bank_number() + * must agree such that the AArch64<->AArch32 SPSRs have the architecturally + * mandated mapping between each other. */ static inline unsigned int aarch64_banked_spsr_index(unsigned int el) { static const unsigned int map[4] = { - [1] = 0, /* EL1. */ + [1] = 1, /* EL1. */ [2] = 6, /* EL2. */ [3] = 7, /* EL3. */ }; |