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| author | Alvise Rigo <a.rigo@virtualopensystems.com> | 2016-01-15 11:37:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-01-15 14:10:02 +0000 |
| commit | deb2db996cbb9470b39ae1e383791ef34c4eb3c2 (patch) | |
| tree | 8c75e3ce109e35f0aa9e41f6e4f5fa0b278c42d4 /target-arm/internals.h | |
| parent | f02ccf53693758b65843264e077f90cf295e7d98 (diff) | |
| download | qemu-deb2db996cbb9470b39ae1e383791ef34c4eb3c2.tar.gz | |
target-arm: Use the right MMU index in arm_regime_using_lpae_format
arm_regime_using_lpae_format checks whether the LPAE extension is used
for stage 1 translation regimes. MMU indexes not exclusively of a stage 1
regime won't work with this method.
In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values
by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1
translation regime.
Rename also the function to arm_s1_regime_using_lpae_format and update
the comments to reflect the change.
Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
Message-id: 1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/internals.h')
| -rw-r--r-- | target-arm/internals.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h index b925aaaa45..d226bbe857 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -441,8 +441,9 @@ struct ARMMMUFaultInfo { bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi); -/* Return true if the translation regime is using LPAE format page tables */ -bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); +/* Return true if the stage 1 translation regime is using LPAE format page + * tables */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual address */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, |