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authorPeter Maydell <peter.maydell@linaro.org>2016-06-17 15:23:46 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-17 15:23:51 +0100
commitbd7d00fc50c9960876dd194ebf0c88889b53e765 (patch)
tree53412e1caa2bbf13ccf8c9376cabd7673ae70a41 /target-arm/internals.h
parent712058764da29b2908f6fbf56760ca4f15980709 (diff)
downloadqemu-bd7d00fc50c9960876dd194ebf0c88889b53e765.tar.gz
target-arm: Provide hook to tell GICv3 about changes of security state
The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be called on such changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-5-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/internals.h')
-rw-r--r--target-arm/internals.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 728ecbab6d..466be0bdad 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -479,4 +479,12 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
int is_user, uintptr_t retaddr);
+/* Call the EL change hook if one has been registered */
+static inline void arm_call_el_change_hook(ARMCPU *cpu)
+{
+ if (cpu->el_change_hook) {
+ cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
+ }
+}
+
#endif