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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:03 +0100 |
| commit | 8bcbf37caa87ba89bc391bad70039f942a98c7e3 (patch) | |
| tree | 94ab31603ae7c7e5b75b42b954d2b803a42c3cc3 /target-arm/translate-a64.c | |
| parent | abf1172fc6dbc9564e25039434d444d9a9f1e88a (diff) | |
| download | qemu-8bcbf37caa87ba89bc391bad70039f942a98c7e3.tar.gz | |
target-arm: Provide correct syndrome information for cpreg access traps
For exceptions taken to AArch64, if a coprocessor/system register
access fails due to a trap or enable bit then the syndrome information
must include details of the failing instruction (crn/crm/opc1/opc2
fields, etc). Make the decoder construct the syndrome information
at translate time so it can be passed at runtime to the access-check
helper function and used as required.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 668916575e..37399df153 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1242,10 +1242,16 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, * runtime; this may result in an exception. */ TCGv_ptr tmpptr; + TCGv_i32 tcg_syn; + uint32_t syndrome; + gen_a64_set_pc_im(s->pc - 4); tmpptr = tcg_const_ptr(ri); - gen_helper_access_check_cp_reg(cpu_env, tmpptr); + syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); + tcg_syn = tcg_const_i32(syndrome); + gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn); tcg_temp_free_ptr(tmpptr); + tcg_temp_free_i32(tcg_syn); } /* Handle special cases first */ |