diff options
| author | Alexander Graf <agraf@suse.de> | 2013-09-03 20:12:09 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-09-10 19:11:28 +0100 |
| commit | 3926cc8433542e8c9b7cdc438355fb7660838fd0 (patch) | |
| tree | e9f54a33589c0828be150d85d0193bf5d6c9cad1 /target-arm/translate.c | |
| parent | 15ee776bf2001883781cc83d456249a60532bb01 (diff) | |
| download | qemu-3926cc8433542e8c9b7cdc438355fb7660838fd0.tar.gz | |
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn't
fit into split up patches. It extends important bits in the core cpu
headers to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag
indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org
[PMM:
* rearranged tbflags so AArch64? is bit 31 and if it is set then
30..0 are freely available for whatever makes most sense for that mode
* added version bump since we change VFP migration state
* added a comment about how VFP/Neon register state works
* physical address space is 48 bits, not 64
* added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 38 |
1 files changed, 29 insertions, 9 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 2d8e0a549f..db7a1d4dd5 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10012,16 +10012,32 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->pc = pc_start; dc->singlestep_enabled = cs->singlestep_enabled; dc->condjmp = 0; - dc->thumb = ARM_TBFLAG_THUMB(tb->flags); - dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags); - dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; + + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + dc->aarch64 = 1; + dc->thumb = 0; + dc->bswap_code = 0; + dc->condexec_mask = 0; + dc->condexec_cond = 0; +#if !defined(CONFIG_USER_ONLY) + dc->user = 0; +#endif + dc->vfp_enabled = 0; + dc->vec_len = 0; + dc->vec_stride = 0; + } else { + dc->aarch64 = 0; + dc->thumb = ARM_TBFLAG_THUMB(tb->flags); + dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags); + dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; + dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; #if !defined(CONFIG_USER_ONLY) - dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); + dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); #endif - dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); + dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); + dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); + dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); + } cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); @@ -10324,6 +10340,10 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos) { - env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos]; + if (is_a64(env)) { + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; + } else { + env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos]; + } env->condexec_bits = gen_opc_condexec_bits[pc_pos]; } |