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| author | Andreas Färber <afaerber@suse.de> | 2013-06-21 21:57:04 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-09 21:33:03 +0200 |
| commit | 5639c3f224bbe3095ce6584bc8a5ace68b6d8197 (patch) | |
| tree | ae234006603c8fdda0827b9d8c14dcad2f55b80f /target-arm/translate.c | |
| parent | 86a35f7c4608b1961a1a459659a97033cc14d274 (diff) | |
| download | qemu-5639c3f224bbe3095ce6584bc8a5ace68b6d8197.tar.gz | |
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index af2aef29e3..9310c586de 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9796,10 +9796,11 @@ undef: /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUARMState *env, +static inline void gen_intermediate_code_internal(ARMCPU *cpu, TranslationBlock *tb, - int search_pc) + bool search_pc) { + CPUARMState *env = &cpu->env; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; uint16_t *gen_opc_end; @@ -10072,12 +10073,12 @@ done_generating: void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(arm_env_get_cpu(env), tb, false); } void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(arm_env_get_cpu(env), tb, true); } static const char *cpu_mode_names[16] = { |