diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-01-04 22:15:44 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-07 19:17:58 +0000 |
| commit | 60322b399dc62da7cc1ccd42fbd19b017f8a5e38 (patch) | |
| tree | 5f18c7d66fc97dbb4a7c74b2a3b8a0ec2dfb8f83 /target-arm/translate.c | |
| parent | f5a0a5a5abe7b72ad14b8884681a25fcf3e91c16 (diff) | |
| download | qemu-60322b399dc62da7cc1ccd42fbd19b017f8a5e38.tar.gz | |
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
This is problematic for the A64 decoder, which doesn't pass the
environment pointer around everywhere the way the 32 bit decoder
does. Adjust the parameters these functions take so that we can
copy only the relevant info from the CPUARMState into the
DisasContext and then use that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 1403ecf216..8bfe95007e 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6498,7 +6498,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; const ARMCPRegInfo *ri; - ARMCPU *cpu = arm_env_get_cpu(env); cpnum = (insn >> 8) & 0xf; if (arm_feature(env, ARM_FEATURE_XSCALE) @@ -6541,11 +6540,11 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) isread = (insn >> 20) & 1; rt = (insn >> 12) & 0xf; - ri = get_arm_cp_reginfo(cpu, + ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2)); if (ri) { /* Check access permissions */ - if (!cp_access_ok(env, ri, isread)) { + if (!cp_access_ok(s->current_pl, ri, isread)) { return 1; } @@ -10269,6 +10268,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); + dc->cp_regs = cpu->cp_regs; + dc->current_pl = arm_current_pl(env); cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); |