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| author | Will Newton <will.newton@linaro.org> | 2014-01-31 14:47:34 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-31 14:47:34 +0000 |
| commit | 664c6733d72c589cd9f6ccee305e7b7ce36ea06d (patch) | |
| tree | 886a26bbf3116ad8144ec50ec34f0d7799d1dac9 /target-arm/translate.c | |
| parent | 7655f39bde5de92b4a3c154a5a8735476c34f458 (diff) | |
| download | qemu-664c6733d72c589cd9f6ccee305e7b7ce36ea06d.tar.gz | |
target-arm: Add support for AArch32 FP VRINTR
Add support for the AArch32 floating-point VRINTR instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 2db681287d..2b3157cabd 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3379,6 +3379,17 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) gen_vfp_F1_ld0(dp); gen_vfp_cmpe(dp); break; + case 12: /* vrintr */ + { + TCGv_ptr fpst = get_fpstatus_ptr(0); + if (dp) { + gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); + } else { + gen_helper_rints(cpu_F0s, cpu_F0s, fpst); + } + tcg_temp_free_ptr(fpst); + break; + } case 15: /* single<->double conversion */ if (dp) gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); |