summaryrefslogtreecommitdiff
path: root/target-arm/translate.c
diff options
context:
space:
mode:
authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-29 00:20:44 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-29 00:20:44 +0000
commitfbb4a2e371f2fa7d3bbe479795d8c79a795f7cd3 (patch)
tree7ac6203fe8fd1adb8b844da4073ae7919bfe83a2 /target-arm/translate.c
parentce5232c5c281552039466be5eadf93a712eb7611 (diff)
downloadqemu-fbb4a2e371f2fa7d3bbe479795d8c79a795f7cd3.tar.gz
Implement ARM magic kernel page and TLS register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 29755de90b..be5b99b079 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8583,7 +8583,16 @@ static inline int gen_intermediate_code_internal(CPUState *env,
store_cpu_field(tmp, condexec_bits);
}
do {
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ /* Intercept jump to the magic kernel page. */
+ if (dc->pc >= 0xffff0000) {
+ /* We always get here via a jump, so know we are not in a
+ conditional execution block. */
+ gen_exception(EXCP_KERNEL_TRAP);
+ dc->is_jmp = DISAS_UPDATE;
+ break;
+ }
+#else
if (dc->pc >= 0xfffffff0 && IS_M(env)) {
/* We always get here via a jump, so know we are not in a
conditional execution block. */