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| author | Will Newton <will.newton@linaro.org> | 2014-01-31 14:47:34 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-31 14:47:34 +0000 |
| commit | 4e82bc01ecc46e90346f731065528b1d47971eba (patch) | |
| tree | 43a44f4a939740c02674dfc7032ed0d76e26e1b4 /target-arm/translate.c | |
| parent | a290c62a7521a5695e12bb9022f8b953c2f50f54 (diff) | |
| download | qemu-4e82bc01ecc46e90346f731065528b1d47971eba.tar.gz | |
target-arm: Add support for AArch32 FP VRINTX
Add support for the AArch32 floating-point VRINTX instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 9afb19fedc..9eb5b929cc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3406,6 +3406,17 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_temp_free_ptr(fpst); break; } + case 14: /* vrintx */ + { + TCGv_ptr fpst = get_fpstatus_ptr(0); + if (dp) { + gen_helper_rintd_exact(cpu_F0d, cpu_F0d, fpst); + } else { + gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpst); + } + tcg_temp_free_ptr(fpst); + break; + } case 15: /* single<->double conversion */ if (dp) gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); |