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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
| commit | 37e6456ef539b2c4d1b9438f3df90eb032a9618f (patch) | |
| tree | d7bc890b4fb05b19f12223ba63bad55005565ee6 /target-arm/translate.h | |
| parent | 394043384337d3e84fe92ecc83bd90b0dcd661d5 (diff) | |
| download | qemu-37e6456ef539b2c4d1b9438f3df90eb032a9618f.tar.gz | |
target-arm: Add support for A32 and T32 HVC and SMC insns
Add support for HVC and SMC instructions to the A32 and
T32 decoder. Using these for real exceptions to EL2 or EL3
is currently not supported (the do_interrupt routine does
not handle them) but we require the instruction support to
implement PSCI.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1412865028-17725-6-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate.h')
| -rw-r--r-- | target-arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/translate.h b/target-arm/translate.h index 85c6f9dcb2..83fbf382a5 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -84,6 +84,8 @@ static inline int get_mem_index(DisasContext *s) #define DISAS_EXC 6 /* WFE */ #define DISAS_WFE 7 +#define DISAS_HVC 8 +#define DISAS_SMC 9 #ifdef TARGET_AARCH64 void a64_translate_init(void); |