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| author | Greg Bellows <greg.bellows@linaro.org> | 2015-05-29 11:28:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-29 11:28:53 +0100 |
| commit | 9dbbc748d671c70599101836cd1c2719d92f3017 (patch) | |
| tree | d62b6b96e7acac84e37e2d1aa0d906617dfcc37a /target-arm/translate.h | |
| parent | 3cf6a0fcedd429693d439556543400d5f0e31e1d (diff) | |
| download | qemu-9dbbc748d671c70599101836cd1c2719d92f3017.tar.gz | |
target-arm: Extend FP checks to use an EL
Extend the ARM disassemble context to take a target exception EL instead of a
boolean enable. This change reverses the polarity of the check making a value
of 0 indicate floating point enabled (no exception).
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
[PMM: Use a common TB flag field for AArch32 and AArch64;
CPTR_EL2 exists in v7; CPTR_EL2 should trap for EL2 accesses;
CPTR_EL2 should not trap for secure accesses; CPTR_EL3
should trap for EL3 accesses; CPACR traps for secure
accesses should trap to EL3 if EL3 is AArch32]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-arm/translate.h')
| -rw-r--r-- | target-arm/translate.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate.h b/target-arm/translate.h index 2eadcb7f06..bcdcf11718 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -22,7 +22,7 @@ typedef struct DisasContext { #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ bool ns; /* Use non-secure CPREG bank on access */ - bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ + int fp_excp_el; /* FP exception EL or 0 if enabled */ bool el3_is_aa64; /* Flag indicating whether EL3 is AArch64 or not */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; |