diff options
| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-19 10:34:35 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-19 10:34:35 +0000 |
| commit | 7997d92f2c75cf56e8142be8e4c1fb5b8dbcc2a4 (patch) | |
| tree | 9b07fba4334e3de4d464ce5760febadd9e0697b2 /target-arm | |
| parent | 22478e79f2793aa1bc7a5019ae2e48303573e0d5 (diff) | |
| download | qemu-7997d92f2c75cf56e8142be8e4c1fb5b8dbcc2a4.tar.gz | |
ARM: fix CPS masks (Vincent Palatin).
According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be 0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 8e3e1695bf..7ba78d9fce 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5813,7 +5813,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) /* Coprocessor double register transfer. */ } else if ((insn & 0x0f000010) == 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10010) == 0x01000000) { + } else if ((insn & 0x0ff10020) == 0x01000000) { uint32_t mask; uint32_t val; /* cps (privileged) */ @@ -5830,7 +5830,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 18)) val |= mask; } - if (insn & (1 << 14)) { + if (insn & (1 << 17)) { mask |= CPSR_M; val |= (insn & 0x1f); } |