diff options
| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-11 12:22:01 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-11 12:22:01 +0000 |
| commit | 868314358ea3f3009fb72d2867dc73af54338ae7 (patch) | |
| tree | a6d9b6d94a727e23847d6554d1fafc865798e425 /target-arm | |
| parent | c96402b11ec09e4b719157409046790bad1f18ca (diff) | |
| download | qemu-868314358ea3f3009fb72d2867dc73af54338ae7.tar.gz | |
Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index bfe0f21353..711676ff7d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -221,8 +221,8 @@ static void store_reg(DisasContext *s, int reg, TCGv var) #define gen_op_rorl_T1_im(im) tcg_gen_rori_i32(cpu_T[1], cpu_T[1], im) /* Value extensions. */ -#define gen_uxtb(var) tcg_gen_andi_i32(var, var, 0xff) -#define gen_uxth(var) tcg_gen_andi_i32(var, var, 0xffff) +#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var) +#define gen_uxth(var) tcg_gen_ext16u_i32(var, var) #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var) #define gen_sxth(var) tcg_gen_ext16s_i32(var, var) @@ -1446,7 +1446,7 @@ static void gen_op_iwmmxt_setpsr_nz(void) static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) { iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_andi_i64(cpu_V1, cpu_V1, 0xffffffffu); + tcg_gen_ext32u_i64(cpu_V1, cpu_V1); tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); } @@ -2704,7 +2704,7 @@ static void gen_neon_dup_u8(TCGv var, int shift) TCGv tmp = new_tmp(); if (shift) tcg_gen_shri_i32(var, var, shift); - tcg_gen_andi_i32(var, var, 0xff); + tcg_gen_ext8u_i32(var, var); tcg_gen_shli_i32(tmp, var, 8); tcg_gen_or_i32(var, var, tmp); tcg_gen_shli_i32(tmp, var, 16); @@ -2715,7 +2715,7 @@ static void gen_neon_dup_u8(TCGv var, int shift) static void gen_neon_dup_low16(TCGv var) { TCGv tmp = new_tmp(); - tcg_gen_andi_i32(var, var, 0xffff); + tcg_gen_ext16u_i32(var, var); tcg_gen_shli_i32(tmp, var, 16); tcg_gen_or_i32(var, var, tmp); dead_tmp(tmp); @@ -5862,7 +5862,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } else { /* MOVT */ tmp = load_reg(s, rd); - tcg_gen_andi_i32(tmp, tmp, 0xffff); + tcg_gen_ext16u_i32(tmp, tmp); tcg_gen_ori_i32(tmp, tmp, val << 16); } store_reg(s, rd, tmp); @@ -6378,10 +6378,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 6)) { /* pkhtb */ tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); + tcg_gen_ext16u_i32(tmp2, tmp2); } else { /* pkhbt */ - tcg_gen_andi_i32(tmp, tmp, 0xffff); + tcg_gen_ext16u_i32(tmp, tmp); tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); } tcg_gen_or_i32(tmp, tmp, tmp2); @@ -7700,7 +7700,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) if (insn & (1 << 23)) { /* movt */ tmp = load_reg(s, rd); - tcg_gen_andi_i32(tmp, tmp, 0xffff); + tcg_gen_ext16u_i32(tmp, tmp); tcg_gen_ori_i32(tmp, tmp, imm << 16); } else { /* movw */ |