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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-02 01:03:34 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-02 01:03:34 +0000 |
| commit | 01d6a890b4dbfa63a6c2e23a768f0e6c9bee55e0 (patch) | |
| tree | 2f88fc70593a1e65ccdb76554be5484a8410102f /target-arm | |
| parent | 6a1cbf68b7cbb6967f218a2cf65345518b49706a (diff) | |
| download | qemu-01d6a890b4dbfa63a6c2e23a768f0e6c9bee55e0.tar.gz | |
Sparc arm/mips/sparc register patch, by Martin Bochnig.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2377 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/exec.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/exec.h b/target-arm/exec.h index 2d2b99aa38..deba89304c 100644 --- a/target-arm/exec.h +++ b/target-arm/exec.h @@ -19,10 +19,17 @@ */ #include "dyngen-exec.h" +#if defined(__sparc__) +struct CPUARMState *env; +uint32_t T0; +uint32_t T1; +uint32_t T2; +#else register struct CPUARMState *env asm(AREG0); register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); register uint32_t T2 asm(AREG3); +#endif /* TODO: Put these in FP regs on targets that have such things. */ /* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */ |