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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:53 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:53 +0100
commit81547d663030cfd3508bc8126d015030ddbe9c96 (patch)
treec24b63b4e7fe11394af77b868daa6b9a20700607 /target-arm
parent3b685ba7bfbecd3e765aff66e67b820653619b7d (diff)
downloadqemu-81547d663030cfd3508bc8126d015030ddbe9c96.tar.gz
target-arm: Register EL3 versions of ELR and SPSR
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-17-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/helper.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a49cf94942..e0f3bb81db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2114,6 +2114,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
+ { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
+ .access = PL3_RW,
+ .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
+ { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
+ REGINFO_SENTINEL
+};
+
static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2368,6 +2381,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_EL2)) {
define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_MPU)) {
/* These are the MPU registers prior to PMSAv6. Any new
* PMSA core later than the ARM946 will require that we