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| author | Greg Bellows <greg.bellows@linaro.org> | 2015-02-05 13:37:21 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-02-05 13:37:21 +0000 |
| commit | 569b49f864e7593a14182acae5a7f5981f6ec24f (patch) | |
| tree | b5ece5e1fd29fb39c0633a17a46a7ff1a746d6f8 /target-arm | |
| parent | 8b47b7da29121ecddb173dd4afb82d6fb0eece37 (diff) | |
| download | qemu-569b49f864e7593a14182acae5a7f5981f6ec24f.tar.gz | |
target-arm: Fix RVBAR_EL1 register encoding
Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1422029835-4696-2-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 1a5e0678b0..c9b1c0824b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; ARMCPRegInfo rvbar = { .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar }; define_one_arm_cp_reg(cpu, &rvbar); |