diff options
| author | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-03-14 01:08:09 +0000 |
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| committer | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-03-14 01:08:09 +0000 |
| commit | 786c02f1acb73ca68ecdc4fa93911495dc1147c6 (patch) | |
| tree | 0af7a4fd67683e1f6531d56c3da62a943b8ee801 /target-cris/cpu.h | |
| parent | e62b5b133b97e07711741e2a4e2bf3e4dbc254f8 (diff) | |
| download | qemu-786c02f1acb73ca68ecdc4fa93911495dc1147c6.tar.gz | |
Model more parts of the ETRAX mmu (still alot missing).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4056 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/cpu.h')
| -rw-r--r-- | target-cris/cpu.h | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 4e92f18d81..31ebaa62ea 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -35,7 +35,7 @@ #define EXCP_MMU_READ 1 #define EXCP_MMU_WRITE 2 #define EXCP_MMU_FLUSH 3 -#define EXCP_MMU_MISS 4 +#define EXCP_MMU_FAULT 4 #define EXCP_BREAK 16 /* trap. */ /* CPU flags. */ @@ -110,9 +110,6 @@ typedef struct CPUCRISState { uint32_t btarget; int btaken; - /* for traps. */ - int trapnr; - /* Condition flag tracking. */ uint32_t cc_op; uint32_t cc_mask; @@ -129,9 +126,12 @@ typedef struct CPUCRISState { int features; - uint64_t pending_interrupts; - int interrupt_request; int exception_index; + int interrupt_request; + int interrupt_vector; + int fault_vector; + int trap_vector; + int user_mode_only; int halted; @@ -245,9 +245,13 @@ static inline int cpu_mmu_index (CPUState *env) #define R_ACR 15 /* Support regs, P0 - P15 */ +#define PR_BZ 0 +#define PR_VR 1 #define PR_PID 2 #define PR_SRS 3 +#define PR_WZ 4 #define PR_MOF 7 +#define PR_DZ 8 #define PR_EBP 9 #define PR_ERP 10 #define PR_SRP 11 @@ -255,12 +259,12 @@ static inline int cpu_mmu_index (CPUState *env) /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 -#define SFR_RW_MM_CFG 1][0 -#define SFR_RW_MM_KBASE_LO 1][1 -#define SFR_RW_MM_KBASE_HI 1][2 -#define SFR_R_MM_CAUSE 1][3 -#define SFR_RW_MM_TLB_SEL 1][4 -#define SFR_RW_MM_TLB_LO 1][5 -#define SFR_RW_MM_TLB_HI 1][6 +#define SFR_RW_MM_CFG 2][0 +#define SFR_RW_MM_KBASE_LO 2][1 +#define SFR_RW_MM_KBASE_HI 2][2 +#define SFR_R_MM_CAUSE 2][3 +#define SFR_RW_MM_TLB_SEL 2][4 +#define SFR_RW_MM_TLB_LO 2][5 +#define SFR_RW_MM_TLB_HI 2][6 #endif |