diff options
| author | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-13 10:59:14 +0000 |
|---|---|---|
| committer | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-13 10:59:14 +0000 |
| commit | cf1d97f07480b6197aebc489938b4e1fed78d3e7 (patch) | |
| tree | d4ae1d25078f714690f5b01761f2bffd5d57f115 /target-cris/cpu.h | |
| parent | 3bd8c5e4f1fdb61a3eb8a4a8b6e5b4cf1156ba76 (diff) | |
| download | qemu-cf1d97f07480b6197aebc489938b4e1fed78d3e7.tar.gz | |
CRIS: Improve TLB management and handle delayslots at page boundaries.
* Dont flush the entire qemu tlb when the $pid changes. Instead we go through
the guests TLB and choose entries that need to be flushed.
* Add env->dslot and handle delayslots at pageboundaries.
* Remove some unused code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4450 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/cpu.h')
| -rw-r--r-- | target-cris/cpu.h | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 845926deda..a26dd80364 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -107,11 +107,10 @@ typedef struct CPUCRISState { /* Pseudo register for the kernel stack. */ uint32_t ksp; - /* These are setup up by the guest code just before transfering the - control back to the host. */ - int jmp; - uint32_t btarget; + /* Branch. */ + int dslot; int btaken; + uint32_t btarget; /* Condition flag tracking. */ uint32_t cc_op; @@ -119,10 +118,8 @@ typedef struct CPUCRISState { uint32_t cc_dest; uint32_t cc_src; uint32_t cc_result; - /* size of the operation, 1 = byte, 2 = word, 4 = dword. */ int cc_size; - /* Extended arithmetics. */ int cc_x_live; int cc_x; @@ -137,13 +134,6 @@ typedef struct CPUCRISState { uint32_t debug2; uint32_t debug3; - struct - { - int exec_insns; - int exec_loads; - int exec_stores; - } stats; - /* FIXME: add a check in the translator to avoid writing to support register sets beyond the 4th. The ISA allows up to 256! but in practice there is no core that implements more than 4. |